1. Field of the Invention
The invention pertains to polishing methods and slurry formulations used in the planarization of integrated circuit surfaces containing various films, most particularly those of a metal, a barrier or liner layer, and a dielectric layer on a semiconductor wafer.
2. Discussion of Related Art
U.S. Pat. No. 5,676,587 discloses a two-step polishing process to be used with Cu interconnect structures. The first step is designed to remove most of the overburden of Cu, and the second step is designed to remove the barrier or liner layer of Ta, TaN, Ti, or TiN. For the second step, a silica based slurry of near-neutral pH is detailed.
One of the problems resulting from polishing a semiconductor wafer by CMP, is that the copper interconnect structures, also known as interconnects, have a surface roughness that exceeds acceptable limits as specified by manufacturing standards. It has been recognized that an excessive surface roughness occurs from the rigors of CMP polishing. A need has existed for a process of polishing a semiconductor wafer that smoothes the surface roughness to acceptable limits. Further, a need has existed for a polishing composition for polishing a semiconductor wafer with interconnects having a surface roughness within acceptable limits.
The invention includes a method for polishing a semiconductor wafer, includes the steps of:
providing a fluid polishing composition with chloride ions,
polishing a barrier layer on the semiconductor wafer with the fluid polishing composition to remove the barrier layer and to polish high points on copper interconnects and solublize copper ions in the polishing composition, and
replating the copper ions from solution with the fluid polishing composition to smooth the surface of the copper interconnects, while the chloride ions migrate near the high points to deter replating of copper ions onto the high points.
By detering such copper replating from the high points, the surface of the copper interconnects become smoothed to have a surface roughness within acceptable limits as specified by manufacturing standards.
Further the invention includes a polishing composition for polishing a semiconductor wafer includes a source of chloride ions in solution that migrate to high points on copper interconnects that are below a polished surface of the semiconductor wafer to deter replating of copper ions from solution onto the high points.
Embodiments of the invention will now be described by way of example with reference to the following detailed description.
One of the requirements in the production of increasingly complex and dense semiconductor structures is the ability to planarize, without which ability, the complexity and density of the structures constructed on a semiconductor wafer are greatly limited. Chemical-Mechanical Planarization, or CMP, is an enabling technology in this area, since it has proved to be the most effective method to planarize surface films on semiconductor substrates.
While the first applications of CMP technology focused on the polishing of dielectric films (i.e., SiO2), polishing of metal structures used for circuit interconnects is increasing rapidly. Along with the increase in metal planarization is an inherent increase in the number of different films that are simultaneously polished. Most metal structures contain three different films: a conductive metal layer, a barrier (or liner) layer between the conductive metal layer and the adjacent dielectric layer, and a dielectric layer. It is often desirable for the removal rates of each film to differ from each other in order to induce planarity and maintain the integrity of the semiconductor structure during polishing. In a typical metal structure, for example, if the entire planarization step were to take place in one step of polishing, it would typically be desirable to have high removal rates of material for the metal and barrier layers, while having low removal rates for the dielectric layer.
However, while it is desirable to limit the number of processing steps, there are often inherent difficulties associated with a one-step process that limit its usefulness. For example, copper interconnects, coupled with low-k dielectrics, have the potential (when compared to Al/SiO2) to increase chip speed, reduce the number of metal layers required, minimize power dissipation, and reduce manufacturing costs. A typical copper interconnect structure contains a conductive copper film, a barrier layer of tantalum or tantalum nitride, and a dielectric layer of silicon dioxide. In one-step copper CMP, it is desirable to remove the Cu and Ta/TaN barrier layer as fast as possible, while removing the SiO2 dielectric layer as slow as possible. However, this is often difficult, since the regimes in which Cu and Ta exhibit comparable removal rates often do not overlap. Also, it is critical to maintain the underlying semiconductor structure regardless of the removal rates of the various films. For the Cu CMP example, the removal of Cu within the interconnect features (called xe2x80x9cdishingxe2x80x9d or xe2x80x9crecessxe2x80x9d) is undesirable since optimal electrical performance is obtained when as much of the conducting metal line as possible remains. Also, it is also desirable to minimize the removal of the SiO2 dielectric layer within interconnect structures (called xe2x80x9cerosionxe2x80x9d).
Farkas et al. in U.S. Pat. No. 5,773,364 presents the use of ammonium salts as oxidizers in metal CMP slurries. Farkas et al. in U.S. Pat. No. 5,614,444 discusses the use of materials with a polar and a polar component in silica-based slurries for the suppression of SiO2 removal rate during metal CMP processes. The use of quaternary ammonium salts as an example of a cationic compound is listed.
U.S. Pat. No. 4,959,113 to Roberts discloses the use of metal chlorides and other metal salts as additives for polishing slurries.
According to an aspect of the invention, chloride ions will bond to a semiconductor surface, and is present as a mobile species able to rapidly move over the surface. These mobile species will equilibrate to specific sites to minimize the energy of the system. These same localized high surface energy sites are the sites where defects initiate. The presence of the chloride ions at these sites decreases the surface energy at these sites to make them essentially indistinguishable from the surface energy at any other site. The uniform surface energy negates localized non-uniform processes and variations in the surface condition of the wafer. Since this is a surface phenomenon, the amount of a compound providing chloride ions necessary to cause this negation of localized variations may be as low as 5 ppm. Preferably the amount of compound used is between 7 and 2000 ppm. Most preferably between 10 and 1000 ppm.
Addition of chloride ions to an aqueous solution composition used for CMP is particularly useful for semiconductor wafers comprising a metal, and is particularly effective when the metal is copper.
Compositions useful in polishing copper typically comprise a complexing agent providing copper ions in solution in the composition, such as citric acid; an inhibitor of initial corrosion, such as benzotriazole; and an organic polymer, such as polyvinyl pyrrolidone. Further, the composition includes an abrasive in the form of colloidal silica particles in fluid suspension, to be used with a polishing pad that is without abrasives. The abrasive is absent from the composition, such that the composition is abrasive free to be used with a polishing pad that itself has abrasives. Use of such additives in a polishing composition is disclosed in U.S. patent application, Ser. No. 09/420,682, filed Oct. 19, 2000, hereby incorporated by reference herein.